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DISCRETE SEMICONDUCTORS
DATA SHEET
BF1105; BF1105R; BF1105WR N-channel dual-gate MOS-FETs
Product specification Supersedes data of 1997 Dec 01 File under Discrete Semiconductors, SC07 1997 Dec 02
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
FEATURES * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier up to 1 GHz. * Internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. APPLICATIONS * VHF and UHF applications with 5 V supply voltage, such as television tuners and professional communications equipment.
page
BF1105; BF1105R; BF1105WR
PINNING PIN 1 2 3 4 DESCRIPTION source drain gate 2 gate 1
Top view
MSB035
handbook, 2 columns 3
4
2
1
BF1105R marking code: NAp.
Fig.2
Simplified outline (SOT143R).
4
3
alfpage
3
4
DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1105, BF1105R and BF1105WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-ss Crss F Xmod Tj PARAMETER drain-source voltage drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation operating junction temperature CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. f = 1 MHz f = 800 MHz Tamb 80 C CONDITIONS MIN. - - - 25 - - - - TYP. - - - 31 2.2 25 1.7 - - MAX. 7 30 200 - 2.7 40 2.5 - 150 UNIT V mA mW mS pF fF dB dBV C
1 Top view
2
MSB014
2 Top view
1
MSB842
BF1105 marking code: NEp.
BF1105WR marking code: NA.
Fig.1
Simplified outline (SOT143B).
Fig.3
Simplified outline (SOT343R).
input level for k = 1% at 40 dB AGC 100
1997 Dec 02
2
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Device mounted on a printed-circuit board. PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature
BF1105; BF1105R; BF1105WR
CONDITIONS - - - - Tamb 80 C; note 1; see Fig.4 -
MIN. 7
MAX. V 30 10 10 200 +150 +150
UNIT mA mA mA mW C C
-65 -
MGM243
handbook, halfpage
250
Ptot (mW)
200
150
100
50
0 0 40 80 120 160 Tamb (C)
Fig.4 Power derating curve.
1997 Dec 02
3
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-s Note 1. Device mounted on a printed-circuit board. STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL V(BR)DSS PARAMETER drain-source breakdown voltage PARAMETER thermal resistance from junction to ambient in free air thermal resistance from junction to soldering point
BF1105; BF1105R; BF1105WR
CONDITIONS note 1
VALUE 350 200
UNIT K/W K/W
CONDITIONS VG1-S = VG2-S = 0; ID = 10 A
MIN. 7 7 7 0.3 8 - -
TYP. - - - 0.8 - - -
MAX. - - - 1.2 16 50 20
UNIT V V V V mA nA nA
V(BR)G1-SS gate 1-source breakdown voltage VG2-S = 0; ID = 0; IG1-S = 10 A V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 A VG2-S (th) IDSX IG1-SS IG2-SS gate 2-source threshold voltage self-biasing drain current gate 1 cut-off current gate 2 cut-off current VG1-S = 5 V; VDS = 5 V; ID = 20 A VG2-S = 4 V; VDS = 5 V VG1-S = 5 V; VG2-S = 0; ID = 0 VG1-S = VDS = 0; VG2-S = 4 V
DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; self-biasing current; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F Gp PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance noise figure power gain f = 1 MHz f = 1 MHz f = 1 MHz f = 800 MHz; YS = YS opt GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt; f = 200 MHz; see Fig.16 GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt; f = 800 MHz; see Fig.17 Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; see Fig.18 CONDITIONS pulsed; Tj = 25 C MIN. 25 - - - - - - - 85 100 TYP. 31 2.2 1.6 1.2 25 1.7 38 20 - - MAX. - 2.7 - - 40 2.5 - - - - UNIT mS pF pF pF fF dB dB dB dBV dBV
reverse transfer capacitance f = 1 MHz
1997 Dec 02
4
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
handbook, halfpage
25
MGM244
ID (mA)
VG1 = 1.7 V
handbook, halfpage
40
MGM245
ID (mA) 30 VG2-S = 4 V 3.5 V 3V 2.5 V
20
1.6 V 1.5 V
15 1.4 V 10 1.3 V 2V 1.2 V 5 1.1 V 1.5 V 1V 0 0 2 4 6 VDS (V) 8 0 0 0.5 1 1.5 2 1V 2.5 VG1 (V) 10 20
VG2-S = 4 V. Tj = 25 C.
VDS = 5 V. Tj = 25 C.
Fig.5 Output characteristics; typical values.
Fig.6 Transfer characteristics; typical values.
MGM246
handbook, halfpage
40
handbook, halfpage
16
MGM247
yfs (mS) 30
VG2-S = 4 V 3.5 V
ID (mA) 12
(1) (2) (3)
3V 20
8
(4) (5)
10
4
2V 0 0 10 20
2.5 V
0
ID (mA)
30
0
1
2
3
4 5 VG2-S (V)
VDS = 5 V. Tj = 25 C.
(1) VDS = 5 V. (2) VDS = 4.5 V. (3) VDS = 4 V.
(4) VDS = 3.5 V. (5) VDS = 3 V.
Fig.7
Forward transfer admittance as a function of drain current; typical values.
Fig.8
Drain current as a function of gate 2 voltage; typical values.
1997 Dec 02
5
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
fMGM248
handbook, halfpage
16
MGM249
handbook, halfpage
16
ID (mA) 12
ID (mA) 12
8
8
4
4
0 0 2 4 6 VDS (V) 8
0
-8
-6
-4
-2
IG1 (A)
0
VG2-S = 4 V. Tj = 25 C.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
Fig.9
Drain current as a function of drain-source voltage; typical values.
Fig.10 Drain current as a function of gate 1 current; typical values.
MGM250
handbook, halfpage
110
Vunw (dBV) 100
90
80 0 20 40 60 gain reduction (dB)
VDS = 5 V; VG2nom = 4 V; IDnom = Iself bias; fw = 50 MHz; funw = 60 MHz; Tamb = 25 C.
Fig.11 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values (see Fig.18).
1997 Dec 02
6
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
102 handbook, halfpage yis (mS) 10
MGM251
103 handbook, halfpage |yrs| (S) 102 rs
MGM252
-103 rs (deg) -102
bis 1 |yrs| 10-1 gis 10
-10
10-2 10
102
f (MHz)
103
1 10
102
f (MHz)
-1 103
VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C.
VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C.
Fig.12 Input admittance as a function of frequency; typical values.
Fig.13 Reverse transfer admittance and phase as a function of frequency; typical values.
102 handbook, halfpage |yfs| (mS) |yfs|
MGM253
-102 fs (deg)
MGM254
handbook, halfpage
10
yos (mS) 1 bos
10
-10 gos 10-1 fs
1 10
102
f (MHz)
-1 103
10-2 10
102
f (MHz)
103
VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C.
VDS = 5 V; VG2-S = 4 V. ID = 12 mA; Tamb = 25 C.
Fig.14 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.15 Output admittance as a function of frequency; typical values.
1997 Dec 02
7
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
handbook, full pagewidth
VAGC 1 nF
VDS
1 nF
2 H 1 nF 1 nF 47 k L2 D BF1105 BF1105R BF1105WR S 10 pF output 50
1 nF 5.5 pF input 50
G2 G1
C1 L1 1 nF
15 pF BB405 330 k 1 nF Vtun input
BB405
330 k 1 nF
Vtun output
MGM255
VDS = 5 V, GS= 2 mS, GL = 0.5 mS, f = 200 MHz. L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire. L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set GL = 0.5 mS. C1 adjusted for GS = 2 mS.
Fig.16 Gain test circuit.
handbook, full pagewidth
VAGC 1 nF
VDS 1 nF
47 k 1 nF 1 nF L1 L2
L3 D BF1105 BF1105R BF1105WR S 1 nF
G2 G1
output 50
input 50
0.5 to 3.5 pF
4 to 40 pF
MGM256
2 to 18 pF
0.5 to 3.5 pF
VDS = 5 V, GS= 3.3 mS, GL = 1 mS, f = 800 MHz. L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane. L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200 nH.
Fig.17 Gain test circuit.
1997 Dec 02
8
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
handbook, full pagewidth
VG2
VDS 4.7 nF
10 k 4.7 nF 10 nF Rgen 50 Vi 50
47 H D S 10 nF
G2 BF1105 BF1105R G1 BF1105WR
R1 = 50
MGM257
Fig.18 Cross-modulation test set-up.
Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2
Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA S11 MAGNITUDE (ratio) 0.994 0.991 0.982 0.968 0.956 0.937 0.918 0.897 0.878 0.858 0.840 ANGLE (deg) -3.8 -7.5 -14.7 -21.7 -28.8 -35.4 -41.8 -48.1 -54.0 -59.9 -65.5 S21 MAGNITUDE (ratio) 3.060 3.047 3.004 2.932 2.896 2.815 2.735 2.651 2.575 2.482 2.396 ANGLE (deg) 175.4 170.9 162.1 153.4 145.3 137.1 129.2 121.5 114.0 106.5 99.5 S12 MAGNITUDE (ratio) 0.000 0.002 0.003 0.004 0.006 0.007 0.007 0.008 0.008 0.008 0.008 ANGLE (deg) 86.9 86.1 82.7 79.7 77.8 76.7 76.3 76.7 79.7 82.2 88.0 S22 MAGNITUDE (ratio) 0.985 0.983 0.980 0.976 0.972 0.967 0.961 0.955 0.948 0.941 0.935 ANGLE (deg) -2.1 -4.2 -8.3 -12.1 -16.2 -20.0 -23.7 -27.3 -30.9 -34.4 -37.9
Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA f (MHz) 800 Fmin (dB) 1.5 opt (ratio) 0.674 (deg) 39.7 Rn () 37.15
1997 Dec 02
9
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
PACKAGE OUTLINES Plastic surface mounted package; 4 leads
BF1105; BF1105R; BF1105WR
SOT143B
D
B
E
A
X
y vMA HE
e bp wM B
4
3
Q
A
A1 c
1
b1 e1
2
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143B
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
1997 Dec 02
10
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
Plastic surface mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y vMA HE
e bp wM B
3
4
Q
A
A1 c
2
b1 e1
1
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT143R
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-03-10
1997 Dec 02
11
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1105; BF1105R; BF1105WR
Plastic surface mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
y
HE e
vMA
3
4
Q
A A1 c
2
wM B bp e1 b1
1
Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 b1 0.7 0.5 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 1.15 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT343R
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 97-05-21
1997 Dec 02
12
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values
BF1105; BF1105R; BF1105WR
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Dec 02
13
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
NOTES
BF1105; BF1105R; BF1105WR
1997 Dec 02
14
Philips Semiconductors
Product specification
N-channel dual-gate MOS-FETs
NOTES
BF1105; BF1105R; BF1105WR
1997 Dec 02
15
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
117067/00/03/pp16
Date of release: 1997 Dec 02
Document order number:
9397 750 03136

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